Reference is now made to FIG. 1 showing a block diagram of a conventional Non-Volatile Memory (NVM) 100. The memory 100 includes a plurality of NVM cells 102 arranged in a memory array 104 including a plurality of rows 106 and a plurality of columns 108.
FIG. 2 shows a circuit diagram of an example NVM cell 102. This circuit is only one example of a NVM cell and it will be understood that other NVM cell circuit configurations could be used. The NVM cell 102 is formed by the series connection of the source-drain paths of an n-channel MOSFET select transistor 116 and an n-channel MOSFET floating gate transistor 118. The NVM cell 102 includes a bit line (BL) terminal 120 coupled to a first end of the series connected source-drain paths (at the drain of the floating gate transistor 118) and a source line (SL) terminal 122 coupled to a second end of the series connected source-drain paths (at the source of the select transistor 116). The gate of the select transistor 116 is coupled to a select line (Sel) terminal 124 of the NVM cell 102 while the top gate of the floating gate transistor 118 is connected to a row word line (WL) with the included floating gate left floating because this terminal is isolated with oxide from both sides.
In a first column 108 of the array, the NVM cells 102 in that column 108 have their source line terminals 122 connected together to a source line 112 of the array and their bit line terminals 120 connected together to a first bit line 110 of the array. In a second column 108 of the array, the NVM cells 102 in that column 108 have their source line terminals 122 connected together to the first bit line 110 of the array and their bit line terminals 120 connected together to a second bit line 110 of the array. Thus, the first bit line 110 of the array acts as the bit line for the NVM cells 102 of the first column 108 and the source line for the NVM cells 102 of the second column depending on configuration set by operation of the column decoder. This arrangement repeats itself across the array until the last column 108 where the NVM cells 102 in that column 108 have their source line terminals 122 connected together to the next-to-last bit line 110 of the array and their bit line terminals 120 connected together to the last bit line 110 of the array.
In this configuration, odd numbered ones of the NVM cells 102 in a given row (for example, NVM cells 102(1) and 102(3)) have their select line terminals 124 connected to a first select line 126(1) for the row 106, while even numbered ones of the NVM cells 102 in that given row (for example, NVM cells 102(2) and 102(n)) have their select line terminals 124 connected to a second select line 126(2) for that same row 106.
The select lines 126 are driven by a row decoder circuit which provides the word lines (not explicitly shown). The source line 112 and bit lines 110 are connected to a column decoder circuit for column selection and sensing by a sense amplifier circuit. The column decoder circuit controls whether a given bit line 110 functions in a bit line mode or a source line mode with respect to a certain column of NVM cells. The column decoder circuit further controls the connection of the source line 112 to ground to support memory array operations.